2008 PARTICIPATING EXHIBITORS

(to date)

 

atrenta_logo

 

Atrenta Inc

Gidel

 

GiDEL

 

jasper

Jasper Design Automation, Inc.

 

mentor

 

Mentor Graphics, Corp.

 

Novas

 

Novas Software

 

nsys_logo

 

nSys, Inc.

 

 

onespin

 

OneSpin Solutions GmbH

 

 

Springer_logo

 

Springer Science & Business Media, LLC

 

synopsys

 

Synopsys, Inc.

 

Consultants' Corner

 

Innovative

 

Innovative Logic

 

DVCon 2008 Call for Papers Deadline

Don't Miss the Deadline:  September 19, 2007

 

The 2008 Design and Verification Conference (DVCon), sponsored by Accellera, is now accepting paper, panel and tutorial submissions.

 

Conference Program            February 19 - 21, 2008

Tuesday, February 19             Tutorials

Wednesday, February 20        Technical Sessions, Panel, Keynote

Thursday, February 21            Technical Sessions, Panel  

 

Exhibition Hours

Tuesday, February 19             4:30pm – 7:30pm

Wednesday, February 20        4:30pm – 7:30pm  

Regular Paper Topic Suggestions:  Call for Papers

 

We encourage you to contribute your experiences with hardware design and verification languages, advance tools and methodologies, and to participate in the valuable exchange of ideas.

  • Experience using ESL and TLM for system-level design and verification
  • Experience with System-on-Chip design
  • Designing and/or verifying complex ASICs and FPGAs
  • Using multiple HDLs and/or HVLs in a design cycle
  • Techniques for generating constrained-random test or other automated stimulus generation methods
  • Synthesizing transaction-level or abstract designs from high-level languages such as SystemC, System Verilog or C++, to RTL
  • Experience with hardware/software co-design and co-verification
  • Experience with mixed-signal simulation
  • Verification techniques that really work (and what did not work)
  • Verification process and resource management
  • Verification methods that have achieved zero functional bugs in first silicon
  • Assertion-based verification
  • Coverage-driven verification
  • Design and verification IP experiences, good and bad
  • Measuring completeness and quality of verification: functional coverage, code coverage or other techniques
  • Experience with formal technologies applied to verification, including the application of model checking and simulation together, or the use of dynamic formal verification tools
  • Any topic involving the use of an HDL or HVL2008

Panel Proposals:  SUBMIT A PANEL NOW! 

Your panel proposal should be a 300-500 word abstract of the panel topic.  Please include a list of proposed panel members.  Be creative with your title!  

 

Sponsored Tutorial Proposals:  DEADLINE: October 3

DVCon is looking for tutorial topics that are current, have a high-level of interest and offer strong education content.  TUTORIAL TOPIC SUGGESTIONS and DEADLINES

 

CONFERENCE SPONSOR

  DVCon is sponsored by Accellera.  Accellera is an industry consortium dedicated to the development and standardization of EDA languages, methods and formats, including design and verification languages. For more information about Accellera, please visit www.accellera.org.